An Analysis Methodology for Dynamic Power Gating

High leakage current in deep-submicrometer designs have become a significant contributor to total power dissipation of CMOS circuits, as short-channel transistors require lower power supply levels to reduce power consumption. This forces a reduction in the threshold voltage that causes a substantial increase of weak inversion current. As evidence of this effect, the 2006 Edition of the International Technology Roadmap for Semiconductors (ITRS) states that “Leakage will become a major industry crisis, threatening the survival of CMOS itself”. Among the leakage-control techniques that have been proposed so far, power gating, also known as MTCMOS, has traditionally been the most effective way to lower the leakage. This article describes a novel dynamic analysis methodology for power gated circuits which can be used as an electrical sign-off method for a full chip in deep sub-micrometer technology. The proposed methodology can achieve spice-comparable accuracy and full-chip-level performance for modern VLSI chip designs.